A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs-Reference-Cited by-同舟云学术

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A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs

Published:2020-01 Issue: Volume:70 Page:60-69
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Li Yanbin,Tang Ming,Li Yuguang,Zhang Huanguo

Funder

National Natural Science Foundation of China

National Basic Research Program of China

Wuhan Science and Technology Project

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference42 articles.

1. Differential power analysis;Kocher,1999

2. Power and electromagnetic analysis: improved model, consequences and comparisons;Peeters;Integr. VLSI J.,2007

3. Overlapped parallel computations of scalar multiplication with resistance against side channel attacks;Al-Somani;Int. J. Inf. Comput. Secur.,2008

4. Towards sound approaches to counteract power-analysis attacks;Chari,1999

5. Block ciphers implementations provably secure against second order side channel analysis;Rivain,2008

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Security Aspects of Masking on FPGAs;2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2024-05-06

2. Deep Learning Gradient Visualization-Based Pre-Silicon Side-Channel Leakage Location;IEEE Transactions on Information Forensics and Security;2024

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