State of the Art

Author:

Posser Gracieli,Sapatnekar Sachin S.,Reis Ricardo

Publisher

Springer International Publishing

Reference52 articles.

1. Abella J, Vera X, Unsal O, Ergin O, Gonzalez A, Tschanz J (2008) Refueling: preventing wire degradation due to electromigration. IEEE Micro 28(6):37–46

2. Balhiser D, Gentry J, Harber R, Haskin B, Marcoux P, Stong G (2005) Process and system for identifying wires at risk of electromigration. US Patent App. 10/241,623. http://www.google.com.br/patents/US20040049750

3. Barwin J, Bickford J (2013) Method of managing electro migration in logic designs and design structure thereof. US Patent 8,560,990. http://www.google.com/patents/US8560990

4. Barwin J, Chung J, Joshi A, Livingstone W, Sigal L, Worth B, Zuchowski P (2015) Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design. US Patent 9,104,832. https://www.google.com/patents/US9104832

5. Butzen PF (2012) Aging aware design techniques and CMOS gate degradation estimative. Ph.D. thesis (doctorate in microelectronics), Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS - Brazil

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