Design and Performance Comparison of Modular Multipliers Implemented on FPGA Platform

Author:

Javeed Khalid,Irwin Daniel,Wang Xiaojun

Publisher

Springer International Publishing

Reference18 articles.

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2. AbdelFattah, A.M., El-Din, A.M.B., Fahmy, H.M.: An efficient architecture for interleaved modular multiplication

3. Blakely, G.: A computer algorithm for calculating the product AB modulo M. IEEE Trans. Comput. C–32(5), 497–500 (1983)

4. Bunimov, V., Schimmler, M., Tolg, B.: A complexity-effective version of Montgomery’s algorithm. In: Workshop on Complexity Effective Designs, ISCA 2002, May 2002

5. Ghosh, S., Mukhopadhyay, D., Chowdhury, D.: High speed Fp multipliers and adders on FPGA platform. In: 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 21–26, October 2010

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