Author:
Wang Ran,Chakrabarty Krishnendu
Publisher
Springer International Publishing
Reference17 articles.
1. K. Kumagai, Y. Yoneda, H. Izumino, H. Shimojo, M. Sunohara, T. Kurihara, M. Higashi, Y. Mabuchi, A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect, in IEEE Electronic Components and Technology Conference, 2008, pp. 571–576
2. S.-Y. Huang, L.-R. Huang, Delay testing and characterization of post-bond interposer wires in 2.5-D ICs, in IEEE International Test Conference (2013)
3. S.-Y. Huang, J.-Y. Lee, K.-H. Tsai, W.-T. Cheng, At-speed BIST for interposer wires supporting on-the-spot diagnosis, in International On-Line Test Symposium (2013)
4. C.-C. Chi, B.-Y. Lin, C.-W. Wu, M.-J. Wang, H.-C. Lin, C.-N. Peng, On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs. IEEE Des. Test 31(4), 16–26 (2014)
5. C.-C. Chi, E.J. Marinissen, S.K. Goel, C.-W. Wu, Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base, in IEEE International Test Conference (2011)