1. Bailey, D.H., et al.: The NAS parallel benchmarks. Int. J. High Perform. Comput. Appl. 5(3), 63–73 (1991)
2. Lecture Notes in Computer Science;C Ballabriga,2010
3. Bell, S., et al.: Tile64-processor: a 64-core soc with mesh interconnect. In: International Solid-State Circuits Conference (ISSCC), pp. 88–598 (2008)
4. Berg, C., Engblom, J., Wilhelm, R.: Requirements for and design of a processor with predictable timing. In: Perspectives Workshop: Design of Systems with Predictable Behaviour. No. 03471 in Dagstuhl Seminar Proceedings (2004)
5. d’Ausbourg, B., Boyer, M., Noulard, E., Pagetti, C.: Deterministic execution on many-core platforms: application to the SCC. In: Many-core Applications Research Community Symposium (MARC), December 2011