Efficient Multitasking on FPGA Using HDL-Based Checkpointing

Author:

Vu Hoang-GiaORCID,Nakada Takashi,Nakashima Yasuhiko

Publisher

Springer International Publishing

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Framework for Live Migration of FPGA based ECB-mode AES-128 accelerator;2022 2nd International Conference on Digital Futures and Transformative Technologies (ICoDT2);2022-05-24

2. Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams;ACM Transactions on Reconfigurable Technology and Systems;2021-09-30

3. Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing;Integration;2021-03

4. SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms;IEEE Access;2021

5. Context Save and Restore of Partial Reconfiguration Regions for Xilinx FPGAs;2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC);2019-07

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