Runtime Adaptive Cache for the LEON3 Processor

Author:

Navarro Osvaldo,Huebner Michael

Publisher

Springer International Publishing

Reference22 articles.

1. Mittal, S.: A survey of architectural techniques for improving cache power efficiency. Sustain. Comput. Inf. Syst. 4(1), 33–43 (2014)

2. Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach. Elsevier, Amsterdam (2011)

3. Silva, B.A., Cuminato, L.A., Bonato, V., Diniz, P.C.: Run-time cache configuration for the LEON-3 embedded processor. In: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015, pp. 42:1–42:6. ACM, New York (2015). https://doi.org/10.1145/2800986.2801026

4. LEON3’s download webpage. grlib-gpl-2017.2-b4164.tar.gz, August 2017. http://www.gaisler.com/index.php/downloads/leongrlib

5. Albonesi, D.H.: Selective cache ways: on-demand cache resource allocation. In: 1999 Proceedings of 32nd Annual International Symposium on Microarchitecture, MICRO-32, pp. 248–259. IEEE (1999)

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1. Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors;2022 IEEE 35th International System-on-Chip Conference (SOCC);2022-09-05

2. A Machine Learning Methodology for Cache Memory Design Based on Dynamic Instructions;ACM Transactions on Embedded Computing Systems;2020-03-17

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