Author:
Fernández-Pascual Ricardo,Ros Alberto,Acacio Manuel E.
Publisher
Springer International Publishing
Reference18 articles.
1. Agarwal, N., Krishna, T., Peh, L.S., Jha, N.K.: GARNET: a detailed on-chip network model inside a full-system simulator. In: IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 33–42, April 2009
2. Alameldeen, A.R., Wood, D.A.: Variability in architectural simulations of multi-threaded workloads. In: 9th International Symposium on High-Performance Computer Architecture (HPCA), pp. 7–18, February 2003
3. Bienia, C., Kumar, S., Singh, J.P., Li, K.: The PARSEC benchmark suite: characterization and architectural implications. In: 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 72–81, October 2008
4. Conway, P., Kalyanasundharam, N., Donley, G., Lepak, K., Hughes, B.: Blade computing with the AMD Opteron™ processor (“Magny Cours”). In: 21st HotChips Symposium, August 2009
5. Cuesta, B., Ros, A., Gómez, M.E., Robles, A., Duato, J.: Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks. In: 38th International Symposium on Computer Architecture (ISCA), pp. 93–103, June 2011
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献