A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs

Author:

Stewart Robert,Michaelson Greg,Bhowmik Deepayan,Garcia Paulo,Wallace Andy

Publisher

Springer International Publishing

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM;Integration;2022-11

2. AnyHLS: High-Level Synthesis With Partial Evaluation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-11

3. HipaccVX: wedding of OpenVX and DSL-based code generation;Journal of Real-Time Image Processing;2020-09-22

4. RIPL;ACM Transactions on Reconfigurable Technology and Systems;2018-03-31

5. Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2018

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