Extraction Tool for the Substrate Network-Reference-Cited by-同舟云学术

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Extraction Tool for the Substrate Network

Published:2018 Issue: Volume: Page:97-112
ISSN:1872-082X
Container-title:Analog Circuits and Signal Processing
language:
Short-container-title:

Author:

Buccella Pietro,Stefanucci Camillo,Kayal Maher,Sallese Jean-Michel

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-74382-0_5

Reference11 articles.

1. H. Ballan, M. Declercq, M. Declercq, in High Voltage Devices and Circuits in Standard CMOS Technologies (Springer, New York, 1999)

2. P. Buccella, C. Stefanucci, H. Zou, Y. Moursy, R. Iskander, J.-M. Sallese, M. Kayal, Methodology for 3-D substrate network extraction for spice simulation of parasitic currents in smart power ICs. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 9, 1489–1502 (2016)

3. F.L. Conte, J.-M. Sallese, M. Pastre, F. Krummenacher, M. Kayal, Global modeling strategy of parasitic coupled currents induced by minority-carrier propagation in semiconductor substrates. IEEE Trans. Electron Devices 57(1), 263–272 (2010)

4. A.F. Franz, G.A. Franz, S. Selberherr, C. Ringhofer, P. Markowich, Finite boxes - a generalization of the finite-difference method suitable for semiconductor device simulation. IEEE Trans. Electron Devices 30(9), 1070–1082 (1983)

5. A. Hastings, The Art of Analog Layout (Prentice Hall, Upper Saddle River, 2005)

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1. CMOS substrate RC netlist reduction towards design cycle speed up;AEU - International Journal of Electronics and Communications;2023-11

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