1. A. Fahim, Clock Generators for SOC Processors: Circuits and Architectures, Boston: Kluwer Academic Publishers, 2005.
2. D. Shaeffer and T. Lee, The Design and Implementation of Low-Power CMOS Radio Receivers, Boston, Kluwer Academic Publishers, 1999.
3. R. Caverly, CMOS RFIC Design Principles, Norwood, MA, Artech House, 2007.
4. T. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993.
5. N. Dalt, et. al., “On the Jitter Requirements of the Sampling Clock for Analog-to-Digital Converters,” IEEE Trans. Circuits and Systems I, vol. 49, no. 9, pp. 1354–1360, September 2002.