Author:
Da Dalt N.,Harteneck M.,Sandner C.,Wiesbauer A.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
70 articles.
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1. Closed-Loop Structure for Mitigating Jitter-Induced Noise of Clock Source in High-Bandwidth Signal Sampling;2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa);2024-05-20
2. Performance Bounds of ADC-Based Receivers Due to Clock Jitter;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-05
3. Channel Estimation and Data Detection in MIMO channels with 1-bit ADC using Probit Regression;2023 IEEE Information Theory Workshop (ITW);2023-04-23
4. Estimating and Tracking Wireless Channels Under Carrier and Sampling Frequency Offsets;IEEE Transactions on Signal Processing;2023
5. Introduction;Synthesis Lectures on Engineering, Science, and Technology;2023