Concealing Secrets in Embedded Processors Designs-Reference-Cited by-同舟云学术

Concealing Secrets in Embedded Processors Designs

Published:2017 Issue: Volume: Page:89-104
ISSN:0302-9743
Container-title:Smart Card Research and Advanced Applications
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Author:

Gross Hannes,Jelinek Manuel,Mangard Stefan,Unterluggauer Thomas,Werner Mario

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-54669-8_6

Reference20 articles.

1. Lecture Notes in Computer Science;C Chen,2016

2. Lecture Notes in Computer Science;T De Cnudde,2016

3. Goodwill, G., Jun, B., Jaffe, J., Rohatgi, P.: A testing methodology for side-channel resistance validation. In: NIST Non-Invasive Attack Testing Workshop (2011)

4. Lecture Notes in Computer Science;L Goubin,1999

5. Lecture Notes in Computer Science;H Gross,2015

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