SRISC: Open Source Soft Processor Side Channel Analysis Attack Framework Using RISC-V

Author:

Jayasinghe Darshana,Parameswaran Sri

Publisher

Springer Nature Switzerland

Reference31 articles.

1. SRISC github repository. (2023). https://github.com/dnjayasinghe/SRISC

2. Lecture Notes in Computer Science;D Agrawal,2003

3. Arora, A., Ambrose, J.A., Peddersen, J., Parameswaran, S.: A double-width algorithmic balancing to prevent power analysis side channel attacks in AES. In: ISVLSI 2013, pp. 76–83 (2013). https://doi.org/10.1109/ISVLSI.2013.6654626

4. Asanović., et al.: The rocket chip generator. Tech. Rep. UCB/EECS-2016-17, EECS Department, University of California, Berkeley (2016). http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html

5. Barthe, L., Benoit, P., Torres, L.: Investigation of a masking countermeasure against side-channel attacks for RISC-based processor architectures. In: FPL 2010, pp. 139–144 (2010)

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