1. Burmaster DE, Hull DA (1997) Using lognormal distributions and lognormal probability plots in probabilistic risk assessments. Hum Ecol Risk Assess 3(2):235–255
2. Butzen PF, Ribas RP (2006) Leakage current in sub-micrometer CMOS gates. Universidade Federal do Rio Grande do Sul, pp 1–28
3. Chang MT, Rosenfeld P, Lu SL, Jacob B (2013) Technology comparison for large last-level caches (L3Cs): low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In: IEEE International symposium on high performance computer architecture (HPCA), pp 143–154
4. Cheng Y, Chan M, Hui K, Jeng Mc, Liu Z, Huang J, Chen K, Chen J, Tu R, Ko PK, et al (1996) BSIM3v3 manual. University of California, Berkeley
5. Chun KC, Jain P, Lee JH, Kim C (2011) A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches. IEEE J Solid State Circuits 46(6):1495–1505