Ion implantation in CMOS Technology: Machine Challenges

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Springer Berlin Heidelberg

Reference15 articles.

1. Brown, D., Tsukihara, M., Ray, A., Splinter, P.: Productivity Comparisons of Various Wafer Scanning Schemes in Ion Implanters, Using Beam Utilization as the Figure of Merit, Proceedings of the Fourteenth International Conference on Ion Implantation Technology (2004).

2. Ghani, T., Mistry, K., Packan, P., Armstrong, M., Thompson, S., Tyagi, S., Bohr, M.: Asymmetric Source/Drain Extension Transistor Structure for High Performance Sub- 50 nm Gate Length CMOS Devices,” VLSI Technology Digest of Technical Papers, 17 (2001).

3. Gossmann, H.-J., Agarwal, A.: Junction Formation in Advanced Planar and Vertical Devices, Proceedings of the Seventh International Conference Solid-State Integrated Circuit Technol (2004).

4. Horsky, T.: Indirectly heated cathode arc discharge source for ion implantation of semiconductors. Rev. of Sci. Instrum. 69(2), 840 (1998).

5. McKenna, C.M.: A Personal Historical Perspective of Ion Implantation Equipment For Semiconductor Applications, Proceedings of the Thirteenth International Conference on Ion Implantation Technology, vol. 1 (2000).

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