Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-540-72685-2_24.pdf
Reference22 articles.
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2. Carrillo, J.E., Chow, P.: The effect of reconfigurable units in superscalar processors. In: Proc. of the ACM/SIGDA FPGA, pp. 141–150 (2001)
3. Clark, N., Blome, J., Chu, M., Mahlke, S., Biles, S., Flautner, K.: An architecture framework for transparent instruction set customization in embedded processors. In: Proc. ISCA, pp. 272–283 (2005)
4. Clark, N., Zhong, H., Mahlke, S.: Processor acceleration through automated instruction set customization. In: MICRO-36 (2003)
5. Hauck, S., Fry, T., Hosler, M., Kao, J.: The Chimaera reconfigurable functional unit. In: IEEE Symp. on FPGAs for Custom Computing Machines, pp. 206–217 (1997)
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