Processor acceleration through automated instruction set customization
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx5/8876/28039/01253189.pdf?arnumber=1253189
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Heterogeneous Multi-core Architectures;IPSJ Transactions on System LSI Design Methodology;2015
2. Customized pipeline and instruction set architecture for embedded processing engines;The Journal of Supercomputing;2014-02-06
3. An algorithm for finding input–output constrained convex sets in an acyclic digraph;Journal of Discrete Algorithms;2012-05
4. Accelerating identification of custom instructions for extensible processors;IET Circuits, Devices & Systems;2011
5. Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration;International Journal of Parallel Programming;2010-01-23
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