1. Mitsuhashi, T., Kuh, E.S.: Power and Ground Network Topology Optimization for Cell-Based VLSIs. In: The Proc. of 29th Design Automation Conference, pp. 524–527 (1992)
2. Huang, S.H., Wang, C.L.: An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints. In: Proc. of IEEE International Symposium on Circuits and Systems, vol. 1, pp. 353–356 (2002)
3. Rabaey, J.M., Pedram, M.: Low Power Design Methodologies. Kluwer Academic Publishers, Dordrecht (1996)
4. Yim, J.S., Bae, S.O., Kyung, C.M.: A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. In: Proc. of Design Automation Conference, pp. 766–771 (1999)
5. Cho, D.S., Lee, K.H., Jang, G.J., Kim, T.S., Kong, J.T.: Efficient Modeling Techniques for IR drop Analysis in ASIC Designs. In: Proc. of the 12th Annual IEEE International ASIC/SOC Conference, pp. 64–68 (1999)