Improving FPGA Performance and Area Using an Adaptive Logic Module-Reference-Cited by-同舟云学术

Improving FPGA Performance and Area Using an Adaptive Logic Module

Published:2004 Issue: Volume: Page:135-144
ISSN:0302-9743
Container-title:Field Programmable Logic and Application
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Author:

Hutton Mike,Schleicher Jay,Lewis David,Pedersen Bruce,Yuan Richard,Kaptanoglu Sinan,Baeckler Gregg,Ratchev Boris,Padalia Ketan,Bourgeault Mark,Lee Andy,Kim Henry,Saini Rahul

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-30117-2_16.pdf

Reference17 articles.

1. Ahmed, Rose, J.: The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density. In: Proc. ACM Symp. FPGAs, pp. 3–12 (2000)

2. Anderson, J., Najm, F., Tuan, T.: Active Leakage Power Optimization for FPGAs. In: Proc. ACM Symp. FPGAs, pp. 33–41 (2004)

3. Betz, V., Rose, J.: Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size. In: Proc. Custom Integrated Circuits Conference, pp. 551–554 (1997)

4. Betz, V., Rose, J., Marquardt, A.: Architecture and CAD for Deep-Subicron FPGAs. Kluwer, Dordrecht (1999)

5. Brown, S., Francis, R., Rose, J., Vranesic, Z.: Field-Programmable Gate Arrays. Kluwer, Dordrecht (1992)

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