Data Reallocation by Exploiting FPGA Configuration Mechanisms-Reference-Cited by-同舟云学术

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Data Reallocation by Exploiting FPGA Configuration Mechanisms

Published: Issue: Volume: Page:312-317
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Sander Oliver,Braun Lars,Hübner Michael,Becker Jürgen

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-78610-8_34.pdf

Reference14 articles.

1. Braun, L., Huebner, M., Becker, J., Perschke, T., Schatz, V., Bach, S.: Circuit switched run-time adaptive network-on-chip for image processing applications. In: Hubner, M. (ed.) Proc. International Conference on Field Programmable Logic and Applications FPL 2007, pp. 688–691 (2007)

2. Blodget, B., McMillan, S., Lysaght, P.: A lightweight approach for embedded reconfiguration of fpgas. In: Proc. Design, Automation and Test in Europe Conference and Exhibition, pp. 399–400 (2003)

3. Lecture Notes in Computer Science;G. Brebner,1996

4. Brebner, G.: The swappable logic unit: a paradigm for virtual hardware. In Proc. 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines 16–18, pp. 77–86, (April 1997)

5. Lecture Notes in Computer Science;A. Donlin,1998

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1. Enabling Dynamic Communication for Runtime Circuit Relocation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-01

2. The First 25 Years of the FPL Conference;ACM Transactions on Reconfigurable Technology and Systems;2017-06-30

3. On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip’s Internal Configuration Infrastructure;ACM Transactions on Reconfigurable Technology and Systems;2015-11-24

4. Reconfigurable Multiprocessor Systems;ACM SIGARCH Computer Architecture News;2014-12-03

5. Verification Challenges;Functional Verification of Dynamically Reconfigurable FPGA-based Systems;2014-07-22

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