Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips
Author:
Publisher
Springer Science and Business Media LLC
Subject
Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software
Link
http://link.springer.com/content/pdf/10.1007/s11390-010-9390-5.pdf
Reference14 articles.
1. Dally W J, Towles B. Route packets, not wires: On-chip interconnection networks. In Proc. 38th ACM Conf. Design Automation, Las Vegas, Nevada, Jun. 18-22, 2001, pp.684–689.
2. Benini L, Micheli G D. Networks on chips: A new SoC paradigm. Computer, 2002, 35(1): 70–78.
3. Wang J L, Xue Y B, Wang H X, Li C M, Wang D S. CCNoC: Cache-coherent network on chip for chip multiprocessors. J. Comput. Sci. & Technol., 2010, 25(2): 257–266.
4. Bainbridge J, Furber S B. CHAIN: A delay-insensitive chip area Interconnect. IEEE Micro, 2002, 22(5): 16–23.
5. Lines A. Asynchronous interconnect for synchronous SoC design. IEEE Micro, 2004, 24(1): 32–41.
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