CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors-Reference-Cited by-同舟云学术

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CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors

Published:2010-03 Issue:2 Volume:25 Page:257-266
ISSN:1000-9000
Container-title:Journal of Computer Science and Technology
language:en
Short-container-title:J. Comput. Sci. Technol.

Author:

Wang Jing-Lei,Xue Yi-Bo,Wang Hai-Xia,Li Chong-Min,Wang Dong-Sheng

Publisher

Springer Science and Business Media LLC

Subject

Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/s11390-010-9322-4.pdf

Reference27 articles.

1. International technology roadmap for semiconductors. http://public.itrs.net , 2009.

2. Tomasevic M, Milutinovic V. Tutorial on the Cache Coherency Problem in Shared-Memory Multiprocessor: Hardware Methods. IEEE CS Press, 1993.

3. http://www-128.ibm.com/developerworks/power/library/paexpert1.html .

4. http://www.intel.com/multi-core/ .

5. http://www.sun.com/processors/throughput/ .

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips;Journal of Computer Science and Technology;2010-09

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