Author:
Li Xiao-Wei,Li Guang-Hui,Shao Ming
Publisher
Springer Science and Business Media LLC
Subject
Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software
Reference30 articles.
1. Anastasakis D, Damiano R, Ma Hi-Keung T, Stanion T. A practical and efficient method for compare-point matching. In Proc. 39th ACM/IEEE Design Automation Conference, New Orleans, 2002, pp. 305?310.
2. Park J, Pixley C, Burns M, Cho H. An efficient logic equivalence checker for industrial circuits. Journal of Electronic Testing: Theory and Applications, 2000, 16(1?2): 91?106.
3. Burch J R, Singhal V. Robust latch mapping for combinational equivalence checking. In Proc. International Conference on Computer Aided Design, San Jose, 1998, pp. 563?569.
4. Shi-Yu Huang, Kwang-Ting Cheng. Formal Equivalence Checking and Design Debugging. Boston: Kluwer Academic Publishers, 1998.
5. Berman C L, Trevillyan L H. Functional comparison of logic designs for VLSI chips. In Proc. IEEE/ACM Int. Conf. Computer-Aided Design, San Jose, California, 1989, pp. 456?459.
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A DEXiRE for Extracting Propositional Rules from Neural Networks via Binarization;Electronics;2022-12-13
2. The complexity of variable minimal formulas;Chinese Science Bulletin;2010-06
3. An ant colony algorithm for minimum unsatisfiable core extraction;Journal of Electronics (China);2008-09
4. SAT-based Bounded Model Checking for SE-LTL;Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD 2007);2007-07
5. Bounded Model Checking of CTL;Journal of Computer Science and Technology;2007-01