1. Metra C et al. Novel technique for testing FPGA. Design, Automation and Test in Europe, Palais des Congres Paris, France, 1998, pp.89–94.
2. Alderighi M, Gummati E, Piuri V, Sechi G. A FPGA based implementation of a fault tolerant neural architecture for photon identification. In Proc. the Int. Symp. Field-Programmable Gate Arrays, Monterey, CA, USA, 1997, pp.166–172.
3. Renovell M, Figueras J, Zorian Y. Test of RAM-based FPGA: Methodology and application to the interconnect. In Proc. 15th VLSI Test Symp., Anaheim, USA, 1997, pp.230–237.
4. Stroud C, Wijesuriya S, Hamilton C, Abramovici M. Built-in self-test of FPGA interconnect. In Proc. the IEEE Int. Test Conf., Washington DC, USA, 1998, pp.404–411.
5. Sun X, Xu J, Trouborst P. Testing Xilinx XC4000 configurable logic blocks with carry logic modules. In Proc. the IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, San Francisco, CA, USA, October 2001, pp.221–229.