A Methodology for Large-Scale Hardware Verification-Reference-Cited by-同舟云学术

A Methodology for Large-Scale Hardware Verification

Published:2000 Issue: Volume: Page:300-319
ISSN:0302-9743
Container-title:Formal Methods in Computer-Aided Design
language:
Short-container-title:

Author:

Aagaard Mark D.,Jones Robert B.,Melham Thomas F.,O’Leary John W.,Seger Carl-Johan H.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-40922-X_17

Reference16 articles.

1. J. Bergeron, Writing Testbenches: Functional Verification of HDL Models, Kluwer Academic Publishers, 2000.

2. T. Kropf, Introduction to Formal Hardware Verification, Springer-Verlag, 1999.

3. Lect Notes Comput Sci;Á. Th. Th. Eirkksson,1998

4. J. O'Leary, X. Zhao, R. Gerth, and C.-J. H. Seger, “Formally verifying IEEE compliance of floating-point hardware,” Intel Technical Journal, First quarter, 1999, Available at developer. http://intel.com/technology/itj/

5. Lect Notes Comput Sci;Y. Xu,1999

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