Processor Directed Dynamic Page Policy

Author:

Huan Dandan,Li Zusong,Hu Weiwu,Liu Zhiyong

Publisher

Springer Berlin Heidelberg

Reference11 articles.

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3. Kanno, Y., et al.: A DRAM System for Consistently Reducing CPU Wait Cycles. In: 1999 Symposium on VLSI Circuits Digest of Technical Papers, pp. 131–132 (1999)

4. Watanabe, T., et al.: Access Optimizer to Overcome the Future Walls of Embedded DRAMs in the Era of Systems on Silicon. ISSCC Digest of Technical Papers, pp. 370–371 (1999)

5. Miura, S., Ayukawa, K., Watanabe, T.: A Dynamic-SDRAM-mode-control Scheme for Low-power Systems with a 32-bit RISC CPU. In: ISLPED 2001, pp. 358–363 (2001)

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1. Dynamic Page Policy Using Perceptron Learning;Proceedings of the 2022 International Symposium on Memory Systems;2022-10-03

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