Design and Implementation of an FPGA-Based Data/Timing Formatter
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-015-5554-0.pdf
Reference20 articles.
1. Altera Corporation (2008) Cyclone II Device Handbook, Volume 1
2. Analog Devices Inc (2007) Quad Pin Timing Formatter ADATE207
3. Bayer E, Traxler M (2010) A high-resolution (< 10 ps RMS) 32-channel time-to-digital converter (TDC) implemented in a field programmable gate array (FPGA). In: Conference Record of IEEE-NPSS Real Time Conference, pp 1–5
4. Bayer E, Zipf P, Traxler M (2011) A multichannel high-resolution (< 5 ps rms between two channels) time-to-digital converter (TDC) implemented in a field programmable gate array (FPGA). In: Conference Record of IEEE Nuclear Science Symposium and Medical Imaging Conference, pp 876–879
5. Carlo SD, Prinetto P, Scionti A, Figueras J, Manich S, Rodriguez-Montanes R (2009) A low-cost FPGA-based test and diagnosis architecture for SRAMs. In: Proceedings of International Conference on Advances in System Testing and Validation Lifecycle, pp 141–146
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2. An FPGA-Based Data Receiver for Digital IC Testing;2019 IEEE International Test Conference in Asia (ITC-Asia);2019-09
3. Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter;2018 IEEE 27th Asian Test Symposium (ATS);2018-10
4. Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation;2017 IEEE 26th Asian Test Symposium (ATS);2017-11
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