Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets
Author:
Funder
National Natural Science Foundation of China
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
https://link.springer.com/content/pdf/10.1007/s10836-023-06064-9.pdf
Reference24 articles.
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2. Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43(6):2874–2878. https://doi.org/10.1109/23.556880
3. Ebara M, Yamada K, Kojima K, Furuta J, Kobayashi K (2019) Process dependence of soft errors induced by alpha particles, heavy ions, and high energy neutrons on flip flops in FDSOI. IEEE J Electron Devices Soc 7:817–824. https://doi.org/10.1109/JEDS.2019.2907299
4. Eftaxiopoulos N, Axelos N, Pekmestzi K (2015) DONUT: a double node upset tolerant latch. 2015 IEEE Computer Society Annual Symposium on VLSI, pp 509–514. https://doi.org/10.1109/ISVLSI.2015.72
5. Fazeli M, Patooghy A, Miremadi SG, Ejlali A (2007) Feedback redundancy: a power efficient SEU-tolerant latch design for deep sub-micron technologies. IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’07), pp 276–285. https://doi.org/10.1109/DSN.2007.51
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