MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs

Author:

Chun Sunghoon,Kim Yongjoon,Kang Sungho

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference11 articles.

1. A. Attarha and M. Nourani, “Test Pattern Generation for Signal Integrity Faults on Long Interconnects,” Proc. IEEE VLSI Test Symp., pp. 336–341, 2002.

2. W. Chen, S.K. Gupta, and M.A. Breuer, “Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Input,” Proc. Int. Test Conf., pp. 809–818, 1997.

3. C. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and Synthesis, New York: Wiley, 2000.

4. M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects,” Proc. Int. Conf. Computer-aided Design, pp. 297–303, 1999.

5. HSPICE, v 2003.03-SP1, Synopsys Corporation.

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