On Built-In Self-Test for Adders

Author:

Pulukuri Mary D.,Stroud Charles E.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units;Microprocessors and Microsystems;2023-06

2. A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block;Engineering Research Express;2023-03-01

3. A Low-Overhead BIST Architecture for Digital Data Processing Circuits;Lecture Notes in Electrical Engineering;2012-08-14

4. A C-Testable Multiple-Block Carry Select Adder;IEICE Transactions on Information and Systems;2012

5. On Built-In Self-Test for multipliers;Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon);2010-03

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