A Layout-Based Rad-Hard DICE Flip-Flop Design
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/article/10.1007/s10836-019-05773-4/fulltext.html
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3. Baze MP, Hughlock B, Wert J, Tostenrude J, Massengill L, Amusan O, Lacoe R, Lilja K, Johnson M (2008) Angular dependence of single event sensitivity in hardened flip/flop designs. IEEE Trans Nucl Sci 55(6):3295–3301
4. Black JD, Sternberg AL, Alles ML, Witulski AF, Bhuva BL, Massengill LW, Benedetto JM, Baze MP, Wert JL, Hubert MG (2005) HBD layout isolation techniques for multiple node charge collection mitigation. IEEE Trans Nucl Sci 52(6):2536–2541
5. Cabanas-Holmen M, Cannon EH, Rabaa S, Amort T, Ballast J, Carson M, Lam D, Brees R (2013) Robust SEU mitigation of 32 nm dual redundant Flip-flops through interleaving and sensitive node-pair spacing. IEEE Trans Nucl Sci 60(6):4374–4380
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