A System-layer Infrastructure for SoC Diagnosis
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-007-5014-6.pdf
Reference41 articles.
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3. Appello D, Bernardi P, Grosso M, Rebaudengo M, Sonza Reorda M, Tancorre V (2006) Embedded Memory Diagnosis: An Industrial Workflow. IEEE Intl Test Conference
4. Appello D, Bernardi P, Grosso M, Rebaudengo M, Sonza Reorda M, Tancorre V (2006) On the Automation of the Test Flow of Complex SoCs. IEEE International VLSI Test Symposium 166–171, May
5. Bardell PH, McAnney WH, Savir J (1987) Built-In Test for VLSI: Pseudorandom Techniques. Wiley Interscience
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2. An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs;2008 13th European Test Symposium;2008-05
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