Testing Disturbance Faults in Various NAND Flash Memories

Author:

Hou Chih-Sheng,Li Jin-Fu

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference17 articles.

1. Cheng KL, Yeh JC, Wang CW, Huang CT, Wu CW RAMSES-FT: a fault simulator for flash memory testing and diagnostics, In Proceedings 20th IEEE VLSI Test Symposium (VTS), 2002, pp. 281–286

2. Carlo SD, Fabiano M, Piazza R, Prinetto P Exploring modeling and testing of NAND flash memories, In East-West Design & Test Symposium (EWDTS), 2010, pp. 17–20

3. Chiu SK, Yeh JC, Huang CT, Wu CW Diagonal test and diagnostic schemes for flash memory, In Proceedings International Test Conference (ITC), 2002, pp. 37–46

4. Cheng KL, Yeh JC, Wang CW, Huang CT, Wu CW RAMSES-FT: a fault simulator for flash memory testing and diagnostics, In Proceedings 20th IEEE VLSI Test symposium (VTS), 2002, pp. 281–286

5. Huang SB, Hsiao CN, Huang CL (2010) Nonvolatile memory cell, U.S. Patent No. 0013062A1

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