Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion-Reference-Cited by-同舟云学术

Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion

Published:2022-08 Issue:4 Volume:38 Page:339-352
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Sun Yang,Millican Spencer K.^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

https://link.springer.com/content/pdf/10.1007/s10836-022-06016-9.pdf

Reference27 articles.

1. Acero C, Feltham D, Liu Y, Moghaddam E, Mukherjee N, Patyra M, Rajski J, Reddy SM, Tyszer J, Zawada J (2017) Embedded Deterministic Test Points. IEEE Trans Very Large Scale Integr VLSI Syst 25(10):2949–2961

2. Brglez F (1984) On Testability Analysis of Combinational Networks. In: Proc IEEE Intl Symp Circuits and Systems (ISCAS), Montreal, Quebec, Canada, May 1984, vol 1, pp 221–225

3. Brglez F, Fujiwara H (1985) A Neutral Netlist of 10 Combinational Benchmark Circuits and a Targeted Translator in FORTRAN. In: Proc. IEEE Intl. Symp. Circuits and Systems (ISCAS), Kyoto, Japan, pp 663–698

4. Chern M et al (2019) Improving Scan Chain Diagnostic Accuracy Using Multi-stage Artificial Neural Networks. In: Proc. 24th Asia and South Pacific Design Automation Conf., Tokyo, Japan, Jan 2019, pp 341–346

5. Davidson S (1999) ITC’99 Benchmark Circuits - Preliminary Results. In: Proc Intl Test Conf (ITC), Atlantic City, NJ, USA, Sep. 1999, p 1125

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