1. Semiconductor industry association (SIA), International technology roadmap for semiconductors (ITRS), 2020,
http://www.siaonline.org/home.cfm
2. Gyepes G, Arbet D, Brenkus J, Stopjakova V, Mihalov J (July 2014) A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays. Microprocess Microsyst 38(5):359–367
3. Gomez AF, Lavratti F, Medeiros G, Sartori M, Bolzani Poehis L, Champac V, Vargas F (2016) Effectiveness of a hardware-based approach to detect resistive open defects in SRAM cells under process variations. Microelectron Reliab 67:150–158
4. Kinseher J, Voelker M, Polian I (2017) Improving testability and reliability of advanced SRAM architectures. IEEE Trans Emerg Top Comput:1
5. L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, M. Hage-Hassan, (2003) “Data retention fault in SRAM memories: analysis and detention procedures.”Proc. of 23
rd
IEEE VLSI Test Symposium(VTS 05) pp.23–28