Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits-Reference-Cited by-同舟云学术

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Published:2008-12-17 Issue:1 Volume:25 Page:117-126
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Al-Assadi Waleed K.,Kakarla Sindhu

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s10836-008-5083-1.pdf

Reference15 articles.

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2. Banerjee S, Chakradhar ST, Roy RK (1996) Synchronous test generation model for asynchronous circuits. Proceedings of the 9th International Conference on VLSI Design 178–185

3. Bandapati SK, Smith SC, Choi M (2003) Design and characterization of NULL convention self-timed multipliers. IEEE Des Test Comput Spec Issue Clockless VLSI Des 30(6):26–36

4. Berkel CH, Rem M, Saeijs R (1998) VLSI programming. 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors 152–156

5. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer Academic, Boston, MA Nov

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