1. Lu SL (2004) Speeding up processing with approximation circuits. Computer 37(3):67–73
2. Zhu N, Goh WL, Wang G, Yeo KS (2010) Enhanced low-power high-speed adder for error-tolerant application Proceedings of the international SoC design conference (ISOCC), pp 323–327
3. Zhu N, Goh WL, Zhang W, Yeo KS, Kong ZH (2010) Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(8):1225– 1229
4. Kulkarni P, Gupta P, Ercegovac M (2011) Trading accuracy for power with an underdesigned multiplier architecture Proceedings of the 24th international conference on VLSI design (VLSID), pp 346–351
5. Zhu N, Goh WL, Wang G, Yeo KS (2010) Enhanced low-power high-speed adder for error-tolerant application Proceedings of the international SoC design conference (ISOCC), pp 323–327