Author:
Ding Chen,Carr Steve,Sweany Phil
Publisher
Springer Berlin Heidelberg
Reference7 articles.
1. Abraham, S., Sugumar, R., Windheiser, D., Rau, B., and Gupta, R. Predictability of load/store instruction latencies. In Proceedings of the 26th International Symposium on Microarchitecture (MICRO-26) (Austin, TX, December 1993), pp. 139–152.
2. Chen, T.-F., and Baer, J.-L. Reducing memory latency via non-blocking and prefetching caches. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (Boston, Massachusetts, 1992), pp. 51–61.
3. Ding, C., Carr, S., and Sweany, P. Software pipelining with cache-reuse information. Tech. Rep. 96-07, Michigan Technological University, Sept. 1996. ftp://cs.mtu.edu/pub/carr/moduto.ps.gz.
4. Lam, M. Software pipelining: An effective scheduling technique for VLIW machines. SIGPLAN Notices 23, 7 (July 1988), 318–328. Proceedings of the ACM SIGPLAN '88 Conference on Programming Language Design and Implementation.
5. McKinley, K. S., Carr, S., and Tseng, C.-W. Improving data locality with loop transformations. ACM Transactions on Programming Languages and Systems 18, 4 (1996), 424–453.
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