Design and Power Analysis of an Ultra-high Speed Fault-tolerant Full-adder Cell in Quantum-dot Cellular Automata

Author:

Bagherian Khosroshahy Milad,Abdoli Alireza,Rahmani Amir MasoudORCID

Publisher

Springer Science and Business Media LLC

Subject

Physics and Astronomy (miscellaneous),General Mathematics

Reference41 articles.

1. Singh, G., Sarin, R.K., Raj, B.: Design and analysis of area efficient QCA based reversible logic gates. Microprocess. Microsyst. 52, 59–68 (2017)

2. AlKaldy, E., Majeed, A.H., Bin Zainal, M.S., Md Nor, B.: Optimum multiplexer design in quantum-dot cellular automata. Indones. J. Electr. Eng. Comput. Sci. 17, 148–155 (2020)

3. Ahmad, F., John, M.U., Khosroshahy, M.B., Sarmadi, S., Bhat, G.M., Peer, Z.A., Wani, S.J.: Performance evaluation of an ultra-high speed adder based on quantum-dot cellular automata. Int. J. Inf. Technol. 11, 467–478 (2019)

4. Abutaleb, M.: A novel power-efficient high-speed clock management unit using quantum-dot cellular automata. J. Nanopart. Res. 19, 128 (2017)

5. Majeed, A.H., Alkaldy, E., bin Zainal, M.S., Nor, B.M.: Synchronous counter design using novel level sensitive T-FF in QCA technology. J. Low Power Electron. Appl. 9, 27 (2019)

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