1. Stephen Brown and J. Rose, “Architecture of FPGAs and CPLDs: A Tutorial,” IEEE Design and Test of Computers, Vol. 13, No. 2, pp. 42–57, 1996.
2. Why reconfigurable computing, Department of Computer Science, Computer Structures Group, http://xputers.informatik.uni-k1.de/.
3. R. Hartenstein, H. Grünbacher (Editors): The Roadmap to Reconfigurable computing Proc.FPL2000, Aug.27–30,2000;LNCS,Springer-Verlag2000.
4. J. R. Hauser and J. Wawrzynek, “Garp: A MIPS Processor with a Re-configurable Coprocessor,” Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
5. A. Abnous, C. Christensen, J. Gray, J. Lenell, A. Naylor and N. Bagherzadeh, “ Design and Implementation of the Tiny RISC microprocessor,” Microprocessors and Microsystems, Vol. 16, No. 4, pp. 187–94, 1992.