Reconfigurable Architecture Using High Speed FPGA

Author:

Kessal L.,Bourguiba R.,Demigny D.,Boudouani N.,Karabernou M.

Publisher

Springer US

Reference6 articles.

1. Didier Demigny, Lounis Kessal, Riad Bourguiba and Nassima Boudouani How to use high speed reconfigurable FPGA for real time image processing ? Proc. International Conf. on Computer Architecture for Machine Perception, pages 240–246, Padova, septembre 2000. IEEE Circuit.

2. Lounis Kessal, Didier Demigny, Nassima Boudouani and Riad Bourguiba. Reconfigurable hardware for real time image processing. Proc. International Conference on Image Processing, volume 3, pages 159–173, Vancouver, septembre 2000. IEEE ICIP.

3. P. Bertin, D. Roncin and J. Vuillemin, Programmable active memories: a performance assessment, In F. Meyer auf der Heide, B. Monien, and A. L. Rosenberg, editors, Parallel Architectures and their efficient use, pp. 119–130, Lecture notes in Computer Science, Springer-Verlag, October 1992.

4. H. Guermoud, Architecure reconfigurables dynamiquement dédiées aux traitements en temps réel des signaux vidéo, Thesis, faculty of Nancy I, France 1997.

5. Riad Bourguiba, Didier Demigny and Lounis Kessal. Dynamic configuration: a new paradigm applied to real time image analysis. In Proc. The tenth International Conference on Microelectronis, pages 25–28, Monas-tir, Tunisia, December 1998. IEEE Electron Device Society.

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