Hardware Synthesis from a Restricted Class of LOTOS Expressions

Author:

Higashino Teruo,Yasumoto Keiichi,Kitamichi Junji,Taniguchi Kenichi

Publisher

Springer US

Reference14 articles.

1. S. W. Director, A. C. Parker, D. P. Siewiorek and D.E. Thomas: “A Design Methodology and Computer Aids for Digital Systems”, IEEE Trans. on Circuits & Systems, 28, 7, pp. 634–645, 1981.

2. M. Faci and L. Logrippo: “Specifying Hardware Systems in LOTOS”, Proc. of Computer Hardware Description Languages and their Applications XI (CHDL’93), pp. 305–312, North-Holland, 1993.

3. M. R. Garey and D. S. Johnson: “Computers and Intractability”, FreeMan, 1979

4. T. Higashino: “Synthesis of Sequential Circuits from a Restricted Class of LOTOS Expressions ”, ICS Research Report, 94-ICS-5, Dept. I.C.S., Osaka Univ., 1994.

5. IEEE: “IEEE Standard VHDL Language Reference Manual”, IEEE, 1988.

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