1. IS8807: Information Processing Systems, Open Systems Interconnection, LOTOS – A Formal Description Technique Based on the Temporal Ordering of Observational Behaviour, ISO, 1989
2. T. Bolognesi, M. Caneve, Equivalence verification: theory, algorithms and a tool, in: The Formal Description Technique LOTOS, Elsevier, Amsterdam, 1989, pp. 303–326
3. Graph-based algorithms for boolean function manipulation;Bryant;IEEE Trans. Comput.,1986
4. Symbolic model checking for sequential circuit verification;Burch;IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems,1994
5. P. Cousot, R. Cousot, Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints, in: Proceedings of the Fourth ACM Symposium on Principles of Programming Languages, Los Angeles, CA, 1997, pp. 238–252