Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning-Reference-Cited by-同舟云学术

Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning

Published:2008 Issue: Volume: Page:25-47
ISSN:1558-9412
Container-title:Adaptive Techniques for Dynamic Processor Optimization
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Author:

Meijer Maurice,Gyvez José Pineda

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-0-387-76472-6_2.pdf

Reference15 articles.

1. Haensch, et al., “Silicon CMOS devices beyond Scaling”, IBM Journal of Research and Development, July/September 2006, Vol. 50, No. 4/5, pp. 339–361

2. D.J. Frank, “Power constrained CMOS scaling limits”, IBM Journal of Research and Development, March/May 2002, Vol. 46, No. 23, pp. 235–244

3. AMD PowerNOW! Technology, AMD white paper, November 2000, http://www.amd.com

4. M. Fleishman, “Longrun power management; Dynamic power management for crusoe processor”, Transmeta white paper, January 2001, http://www.transmeta.com

5. S. Gochman, et al., 01C;The Intel Pentium M processors: Microarchitecture and performance”, l Technology Journal, May 2003, Vol. 7, No. 2, pp. 22–36

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