FPGA and ASIC Implementations of AES-Reference-Cited by-同舟云学术

FPGA and ASIC Implementations of AES

Published:2009 Issue: Volume: Page:235-294
ISSN:
Container-title:Cryptographic Engineering
language:
Short-container-title:

Author:

Gaj Kris,Chodowiec Pawel

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-0-387-71817-0_10.pdf

Reference45 articles.

1. FIPS 197: Advanced Encryption Standard. National Institute of Standards and Technology, 2001, available at http://csrc.nist.gov/publications/ fips/fips197/fips-197.pdf

2. Amphion. Documentation of cryptographic cores, available at http://www . amphion.com

3. D. Canright. A very compact Rijndael S-box. Technical Report NPS-MA-05-001, 2005.

4. D. Canright. A very compact S-box for AES. In J. R. Rao and B. Sunar, editors, Proc. International Workshop on Cryptographic Hardware and Embedded Systems (CHES’05), LNCS, vol. 3659, pp. 441–455. Springer-Verlag, 2005.

5. P. Chodowiec. Comparison of the hardware performance of the AES candidates using reconfigurable hardware. Master’s thesis, George Mason University, Mar. 2002.

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Deep Learning Gradient Visualization-Based Pre-Silicon Side-Channel Leakage Location;IEEE Transactions on Information Forensics and Security;2024

2. A New Fast and Side-Channel Resistant AES Hardware Architecture;2023 IEEE International Conference on Cyber Security and Resilience (CSR);2023-07-31

3. Shared Round Core Architecture: A Novel AES Implementation for Implantable Cardiac Devices;2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS);2022-08-07

4. Implementation of XTS - GOST 28147-89 with Pipeline Structure on FPGA;Modelling, Computation and Optimization in Information Systems and Management Sciences;2021-12-08

5. An efficient AES implementation using FPGA with enhanced security features;Journal of King Saud University - Engineering Sciences;2020-02