Shared Round Core Architecture: A Novel AES Implementation for Implantable Cardiac Devices

Author:

Davis Cory1,John Eugene1

Affiliation:

1. University of Texas San Antonio,Dept. of Electrical & Computer Engineering,San Antonio,United States of America

Publisher

IEEE

Reference13 articles.

1. A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices

2. Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET

3. A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS

4. A compact, ultra-low power AES-CCM IP core for wireless body area networks;hoang;2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC),2016

5. Pacemaker;Mayo Clinic,2018

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. The Security Evaluation of an Efficient Lightweight AES Accelerator;Cryptography;2024-06-04

2. Novel High Throughput-to-Area Efficiency and Strong-Resilience Datapath of AES for Lightweight Implementation in IoT Devices;IEEE Internet of Things Journal;2024-05-15

3. Securing an Efficient Lightweight AES Accelerator;2023 IEEE 22nd International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom);2023-11-01

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