1. Hayashi, Y.: Impacts of Low-k Film on Sub-100 nm-node, ULSl Devices. IEEE Intl. Interconnect Tech. Conf., (San Francisco, USA), 145 (2002)
2. Maex, K.; Baklanov, M.R.; Shamiryan, D.; Lacopi, F.; Brongersma, S.H.; Yanovitskaya, Z.S.: Low dielectric constant materials for microelectronics. J. Appl. Phys, 93(11), 8793 (2003)
3. Abe, M.; Tada, M.; Ohtake, H.; Furutake, N.; Narihiro, M.; Arai, K.; Takeuchi, T.; Saito, S.; Taiji, T.; Motoyama, K.; Kasama, Y.; Arita, K.; Ito, F.; Yamamoto, H.; Tagami, M.; Tonegawa, T.; Tsuchiya, Y.; Fujii, K.; Oda, N.; Sekine M.; and Hayashi, Y.: A robust 45 nm-node, dual damascene interconnects with high quality cu/barrier interface by a novel oxygen absorption process. IEEE Intl. Electron Device Meeting, Tech. Washington DC, USA, Digest, 77 (2005)
4. Ogawa, E.T.; McPherson, J.W.; Rosal, J.A.; Dickerson, K.J.; Chiu, T.–C.; Tsung, L.Y.; Jain, M.K.; BonifieldT.D.; and Ondrusek, J. C.: Stress-induced voiding under vias connected to wide Cu metal leads. Proc. IEEE 40th Annual Intl. Reliability Physics Symp. San Jose, USA, 312 (2002)
5. Abe, M.; Furutake, N.; Saito, S.; Inoue N.; and Hayashi, Y.: Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects. Japanese J Appl. Phys. 44(4B), 2294 (2005)