Test Strategies for Gated Clock Designs-Reference-Cited by-同舟云学术

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Test Strategies for Gated Clock Designs

Published:2009-08-13 Issue: Volume: Page:273-293
ISSN:
Container-title:Power-Aware Testing and Test Strategies for Low Power Devices
language:
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Author:

Keller Brion,Chakravadhanula Krishna

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-1-4419-0928-2_9.pdf

Reference26 articles.

1. Agarwal K, Vooka S, Ravi S, Parekhji R, Gill AS (2008) Power analysis and reduction techniques for transition fault testing. Proc Asian Test Symp 403–408

2. Benini L, Siegel P, De Micheli G (1994) Saving power by synthesizing gated clocks for sequential circuits. IEEE Design Test Comp 11(4):32–41

3. Chickermane V, Gallagher P, Sage J, Yuan P, Chakravadhanula K (2008) A power-aware test methodology for multi-supply multi-voltage designs. Proc Int Test Conf, Paper 9.1

4. Czysz D, Kassab M, Lin X, Mrugalski G, Rajski J, Tyszer J (2008) Low power scan shift and capture in the EDT environment. Proc Int Test Conf, Paper 13.2

5. Donno M, Macii E, Mazzoni L (2004) Power-aware clock tree planning. Proc Int Symp Phys Design 138–147

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