Author:
Goel Sandeep Kumar,Chakrabarty Krishnendu
Reference80 articles.
1. V. D. Agrawal, C. R. Kime and K. K. Saluja, “A tutorial on Built-In Self-Test, Part 1: Principles,” IEEE Design and Test of Computers, vol. 10, no. 1, pp. 73–82, 1993a.
2. V. D. Agrawal, C. R. Kime and K. K. Saluja, “A tutorial on Built-In Self-Test, Part 2: Applications,” IEEE Design and Test of Computers, vol. 10, no. 2, pp. 69–77, 1993b.
3. A. Al-Yamani, E. Chmeler, and M. Grinchuck, “Segmented addressable scan architecture,” Prof. IEEE VLSI Test Symposium, pp. 405–411, May 2005.
4. N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A. Virazel, S. Pravossoudovitch, and C. Landrault, “A selective scan slice encoding technique for test data volume and test power reduction,” Journal of Electronic Testing: Theory and Applications, vol. 24, pp. 353–364, August 2008.
5. D.H. Baik and K.K. Saluja, “Progressive random access scan: A simultaneous solution to test power, test data volume and test time,” Proc. IEEE International Test Conference, pp. 1–10, November 2005.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献